This application claims the priority benefit of Taiwan application serial no. 90127398, filed on Nov. 5, 2001.
1. Field of Invention
The present invention relates to a fabrication method for an integrated circuit device. More particularly, the present invention relates to a fabrication method for a non-volatile memory with a shallow junction.
2. Description of Related Art
Memory devices are widely used in a myriad of applications. A memory device typically includes several thousand of memory cells organized in an array, arranged in rows and columns. Memory cells in the same row or the same columns are coupled by a common wiring line, known as a word line. The vertical wiring line related to data transmittance is called a bit line. A common structure of a memory device consists of an array of memory cells positioned at the intersections between an array of parallel buried conducting lines formed in a semiconductor substrate and a perpendicular array of conductive wiring forms above the substrate. A prominent example of such a memory structure is read-only memory (ROM). Read-only memory is a non-volatile semiconductor memory widely used in computer and microprocessor systems for permanently storing information that is repeatedly used. A few samples of read-only memory include programmable ROMs (PROM), erasable programmable ROMs (EPROM), electrically erasable programmable ROMs (EEPROM) and flash EEPROM.
Conventional ROMs are formed by an array of MOSFETs (metal-oxide semiconductor field-effect transistors), each MOSFET being associated with one single memory cell of the ROM device. A typical ROM device is formed with a plurality of substantially parallel spaced diffusion regions which serve as an array of buried bit lines. An array of word lines is formed to extend over the surface of the substrate in a direction generally perpendicular to the array of buried bit lines. The intersections between the bit lines and the word lines are the locations where the memory cells of the ROM device are formed. Most often, the bit lines of the ROM device act as the source/drain regions for the memory field-effect transistors.
As the demand for high-density memory increases, the integrated circuit industry has been progressed to make semiconductor elements smaller and smaller in order to achieve ultra high density semiconductor devices. As transistors disposed on integrated circuits become smaller, transistors with shallow source/drain extensions have become more difficult to manufacture.
Typically, the technique for fabricating a shallow doped region include the used of an ion beam to shallowly implant a dopant into the semiconductor substrate. As is well known to those skilled in the art, the ion implantation process generally operates by ionizing and accelerating dopant atoms into the semiconductor substrate. The dopant atoms are thereby implanted into the semiconductor substrate. The application of the conventional ion implantation techniques in forming source/drain extensions with shallow junction depths make transistors susceptible to short channel effects. Also the ion implantation process often damages the crystal lattice of the semiconductor substrate being implanted. In the case of a shallow doped region, ion implantation damage generally has a greater adverse affect because the size of the doped region is small. For example, damage to the source and drain regions may result in an increase in the leakage and in a roll-off effect due to the threshold voltage of the transistor, thereby decreasing the performance of the transistor. Moreover, point defects generated in the semiconductor substrate during ion implantation can cause the dopant to diffuse more easily (transient enhanced diffusion, TED). The diffusion often extends the source/drain extensions vertically into the semiconductor substrate. Shallow source/drain extensions are thus difficult to maintain.
The present invention provides a fabrication method for a non-volatile memory with a shallow junction, wherein the shallow junction is formed by solid state diffusion to prevent the aforementioned problems occurring in the prior art.
The non-volatile memory with a shallow junction formed according to the present invention includes forming a plurality of liner stack structures in a memory cell region, wherein each liner stack structure comprises an electron-trapping layer and a conductive layer. A plurality of doped spacers is formed on the sidewalls of the liner stack structures. Thereafter, buried bit lines are formed in the substrate between the liner stack structures. Thermal process is conducted to cause the dopant to diffuse from the doped spacers into the substrate, adjacent to the buried bit lines.
Accordingly, the shallow junction of the present invention is formed without the conventional ion implantation technique. Damages to the crystal lattice of the semiconductor substrate being implanted are mitigated. An increase in the current leakage and in a roll-off effect due to the threshold voltage of the transistor, leading to a decrease of the transistor""s performance is thereby obviated. Moreover, point defects generated in the semiconductor substrate during ion implantation, causing dopant to diffuse more easily and more extensively into the semiconductor substrate are also prevented to maintain the shallow source/drain extensions.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.